To simplify the following discussion, the present invention will be discussed in the context of ferroelectric-based memory elements; however, it will be apparent from the following discussion that the present invention may be utilized in a variety of circuits based on ferroelectric devices. Non-volatile memories based on ferroelectric materials have been known to the art for many years. In their simplest form, such memories are based on a storage cell consisting of an isolation transistor and a capacitor having a ferroelectric dielectric layer. Information is stored in the capacitor dielectric by applying voltages that set the polarization of the dielectric layer, a polarization in one direction denoting a 1, and a polarization in the other direction denoting a 0. The isolation transistor connects or disconnects the capacitor to a bit line used to communicate the read and write signals involved in reading and writing the state of the capacitor.
Ferroelectric-based non-volatile memories provide faster write times than non-volatile memories based on EEPROM or flash memory technologies. In addition, ferroelectric-based memories may be re-written millions or even billions of times; whereas, EEPROM and flash memories are limited to typically 10,000 writes. The write limitation prevents EEPROM and flash memories from being used in a number of applications.
While the basic design and advantages of ferroelectric-based memories have been known for more than a decade, commercial devices based on this technology are still lacking. Memories based on ferroelectric devices are normally constructed in a two step process in which the ferroelectric-based capacitor is constructed over a substrate in which the isolation transistors have been fabricated using conventional CMOS technology. After the isolation transistors and other logic circuitry are fabricated on the silicon substrate by conventional semiconductor fabrication techniques, a dielectric layer, typically glass, is deposited over the substrate to protect this circuitry from damage during the subsequent capacitor fabrication steps.
The dielectric layer includes vias for making connections to the underlying silicon-based components. The connections are provided by conducting “plugs” that are deposited in these vias. The resistance of this connection contributes to the overall RC time constant, which, in turn, determines the time needed to read data from the device. The resistance is related to the aspect ratio of the vias. Hence, it is advantageous to provide vias with as large a diameter as possible to minimize the conductivity of this connection. However, large diameter vias limit the degree to which memory cells can be packed on the substrate. Accordingly any improvement must rely on finding higher conducting materials for the plugs.
In addition to providing high conductivity, the plug material must withstand the processing temperatures involved in the fabrication of the capacitors. These temperatures typically exceed 650° C. Hence, highly conductive materials such as aluminum cannot be utilized for the plugs unless the circuit design can be arranged such that the plug layers are deposited after the high processing steps. Unfortunately, such designs require the capacitors to be fabricated next to the isolation transistors as opposed to being fabricated over the isolation transistors, which increases the size of the memory cells.
Accordingly, platinum or polysilicon are the conductors of choice in prior art memory designs. While platinum electrodes and connections have been used in the prior art, the platinum causes other problems in subsequent processing. After the devices have been fabricated, the finished devices are subjected to processing steps in which the devices are exposed to hydrogen at elevated temperatures. The platinum catalyzes the breakdown of the hydrogen gas into H+ ions that damage the ferroelectric dielectric. While the damage can be corrected by subsequent processing, this processing increases the cost of the devices and places additional constraints on the device design. Accordingly, it would be advantageous to be able to avoid the use of platinum in the devices.
In prior art capacitor fabrication steps, the high processing temperatures also damage the underlying CMOS circuitry to some extent. This damage reduces device yield, and hence, increases the cost of ferroelectric-based memories. The extent of the damage depends both on the processing temperatures and the length of time at which the devices are held at these temperatures. Hence, it would be advantageous to provide a fabrication system and/or device design in which both the maximum processing temperature and the exposure time are reduced.
Broadly, it is the object of the present invention to provide an improved ferroelectric-based memory and method of making the same.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.